1. Field of the Invention
The invention relates in general to systems for testing integrated circuits and in particular, to a system for functionally testing the logic of an integrated circuit that communicates through both synchronous digital signals and through one or more high speed asynchronous serialization/de-serialization (serdes) buses.
2. Description of Related Art
Digital integrated circuits (ICs) typically communicate through digital signals in which edges are synchronized to edges of clock signals. Conventional digital IC testers typically employ a separate channel to access each pin of an IC device under test (DUT), and each channel may either send a test signal to a DUT pin or sample a DUT output signal produced at a DUT pin. The tester organizes the test into a succession of test cycles a pattern generator in each channel generates a multiple-bit data word (a “vector”) before the start of each test cycle encoded to indicate whether the channel is, for example, to drive a signal high or low during the test cycle or is to sample the DUT output signal to determine whether it is of some expected state. The vector will also indicate the times during each test cycle at which the state change or sampling events are to occur and may indicate an expected state of the DUT output signal sample. When the IC tester supplies the DUT with the clock signals that the DUT uses to control the timing of signal edges it produces, then all of the state changes in each DUT output signal should occur at predictable times relative to those clock signals if the DUT is operating properly. Therefore, when a test engineer develops the vector sequences for controlling channel behavior during a test, the test engineer will be able to control the DUT's timing through the vector sequences controlling its input clock signal(s), and will be able to control the timing of the DUT's input data signals through vector sequences controlling those data signals. This enables the test engineer to predict when the DUT's output signals will change state, if the DUT operates as expected, thereby enabling the test engineer to design the vector sequences controlling the timing with which the DUT's output signals are sampled during each test cycle and indicating expected states of those signals.
Many ICs now include one or more ports that communicate through serialization/deserialization “serdes” buses. In “source synchronized” serdes communications systems, a transmitting IC sends a clock signal to the receiver along with the serial data signal to tell the receiver when to sample the data signal. In “embedded clock” serdes communication systems, the transmitter does not send a clock signal with the data signal and the receiver must recover the transmitter's clock signal (i.e., determine he the phase and frequency of the transmitter's clock signal) by monitoring the timing of edges of the incoming data signal. In either case, the receiving IC requires time to synchronize its receiving clock signal to the transmitting IC's clock signal before the transmitting IC begins transmitting data. The amount of time required is variable and unpredictable.
Although we might like to use an IC tester channel to directly sample a serdes signal transmitted by the DUT, a conventional IC tester channel is not adapted to synchronize its sampling clock to the DUT's clock signal when the DUT and tester clock signals are independent and of potentially different frequencies and phases. Also, when multiple serdes systems operate in parallel to produce higher data rates, synchronization requires aligning the phase of the multiple serdes signals to align not only timing but also the data bits. Such alignment is accomplished during an asynchronous training sequence, an interaction between the transmitter and the receiver occurring in a manner that is not deterministic from DUT to DUT.
A serdes signal that is synchronized to a clock signal will exhibit some amount of “jitter” in that the timing of its edges will continuously vary with respect to the timing of edges of the clock signal. When testing a DUT receiving a serdes signal it is desirable to test whether it can tolerate some specified amount of jitter in that signal and to measure the jitter in its output signal to determine whether it is within acceptable limits.
What is needed is an IC tester architecture that allows an IC tester to carry out a functional test on a DUT that communicates through tester-synchronous, deterministic digital signals as well as through source-synchronous serdes buses. The IC tester should also be able to conduct jitter testing on an IC port.